Cadence Put Agents Inside Chip Design and Cut a Five-Week Verification Cycle to a Day

Chip design has a labour problem that money cannot fix quickly. Cadence's own account of it, given by a vice president of global customer success, is that the work keeps expanding and the industry cannot hire fast enough. So the company spent this year building agents that do the work instead, and in September it started publishing what they returned.

Four super agents, one orchestration layer

Cadence has launched four autonomous "super agents." ChipStack covers automated digital RTL design and verification. ViraStack handles custom analog layout generation. InnoStack covers digital implementation and physical signoff closure. AuraStack takes PCB design and 3D-IC packaging. AgentStack sits above them as the orchestration framework and head agent, so a single workflow can pass a task from one specialist agent to another.

On 22 September the company added an RTL Generation Agent to ChipStack. It takes a high-level specification and produces production-ready RTL optimised for power, performance and area, then analyses and refines it, all driven from natural language prompts. It also handles updates to existing RTL, letting a customer describe a new requirement at a high level and have the agent carry out the change while checking that power, performance and function still hold. In early evaluations Cadence reports an average 24 percent area reduction and 18 percent power reduction against code produced by a foundation model alone, with what it describes as 100 percent functionally accurate RTL. Honda is evaluating the tool on advanced automotive SoCs, where safety requirements and tight power envelopes leave little room for a plausible-looking answer that does not work.

The numbers that are already in production

The verification figure is the one to hold onto. Cadence says ChipStack has more than twenty customer projects and is deployed in production across multiple chip designs, and that early customers have seen RTL validation run more than 40 times faster, taking a typical five-week verification cycle to less than a day on an advanced node design.

ViraStack has more than 25 customer engagements with reported gains of two to ten times in analog and custom design. AuraStack is quoted at up to 15 times higher productivity and twice the speed to market for PCB and packaging work. One automotive supplier, Forvia Hella, reduced a component placement task from four days to about four minutes.

Those are vendor numbers and should be read as such. They are also unusually specific, which makes them checkable in a way that a productivity percentage usually is not. A five-week cycle is a number a customer already tracks.

Why agents increase tool usage instead of reducing it

The obvious fear in this market is that good agents eat the tools underneath them. Cadence's chief executive, Anirudh Devgan, argues the opposite, and the argument is worth following because it contradicts the usual story about AI compressing software revenue.

His version is that a human designer can run three or four experiments at a time, while an agent can run a hundred. Agents therefore call more of the underlying engines, not fewer. Cadence's agentic business runs on a consumption plus subscription model, while the middle layer of EDA tools keeps its existing commercial terms. Customers buying agents do not stop buying the software the agents drive.

The second half of the argument is about workload. Devgan's comparison is that designing a CPU once took 500 people five years, and now takes 30 to 40 people six months. Design efficiency improved by roughly a hundredfold, and total design activity still went up, because AI training and inference keep creating demand for new chips at new nodes.

That is why the talent gap is the pitch rather than a side note. If the industry genuinely cannot hire enough engineers, agents that expand the effective size of a team are the only lever that moves this year. The same pressure is why Cadence's IP business grew more than 40 percent year over year, with demand concentrated in PCIe, UCIe, HBM and LPDDR6 interfaces, and why its hardware business, built on the Palladium Z3 and Protium X3 platforms, had a record quarter. Verification capacity is becoming a strategic resource rather than a line item.

The hierarchy the company built

Cadence's description of the architecture is that super agents orchestrate task-specific agents, and those agents call the company's own EDA software, which has been tuned for agentic use. That three-layer design is why the company can point at customer engagement counts rather than at a single pilot, and why it argues that domain agents beat a general model pointed at the same job. InnoStack, which covers digital implementation and physical signoff closure, is earlier in that process, and Cadence says it is building momentum as customers adopt agentic workflows for advanced-node SoC design.

Domain specificity is the technical claim

The interesting engineering claim is not that the agents work. It is why Cadence thinks they hallucinate less than a general model pointed at the same task.

Cadence's answer is depth of access. A generic agent sees tool outputs and reasons over reports and logs. Cadence owns the core engines the tools run on, so its agents can be built with hooks below the output layer, which lets the company target determinism rather than plausibility. The framing from the customer success team is that the agents raise the abstraction by one level: the engineering work moves to the agent, and the designer moves to judgement.

The ecosystem work supports that story. Cadence lists NVIDIA, TSMC, Socionext and Schneider Electric among companies deploying its agentic workflows for packaging and PCB design. It has a multi-year engagement with Intel around the 14A process, deepened work with Samsung Foundry on two-nanometre and 3D IC technology, and agreed with Rapidus to integrate InnoStack into that company's agent design solution, targeting up to twice the design turnaround.

That claim will be tested by the market rather than by a benchmark. Synopsys shipped its own agentic engineering workflow in March 2026, claiming up to twice the productivity and five times in some cases. Both companies are selling the same idea, which is that chip design is a flow rather than a prompt, and that the value sits in knowing the flow.

The expanded ChipStack and InnoStack capabilities are expected to reach select early-access customers in the fourth quarter of 2026. Cadence reported second-quarter revenue growth of 24 percent and a backlog of 8.1 billion dollars, and raised its full-year growth expectation to 19 percent. A company with a backlog that size can afford to let the agents be judged on yield and power rather than on a demo, which is the right test anyway. A design that verifies in a day instead of five weeks is only useful if the silicon that comes out of the flow meets its power target, and that is a claim no benchmark harness will settle.